Digital delay line

ABSTRACT

A digital delay line including a first feedback delay line having a first number of interlinked first delay elements, at least one second feedback counter having a second number of second interlinked counting elements, the counting elements being clocked by one of the first delay elements.

FIELD OF THE INVENTION

The present invention relates to the field of digital delay lines,particularly for use for radar-based distance measurements andrelative-speed measurements from a vehicle.

BACKGROUND INFORMATION

As to the use of analog delay lines for radar sensors, one such delayline is made up of a number of discrete components. Charging times anddischarging times of capacitors or coils are used in a complicatedinterconnection for producing the delay.

Also available is a digital delay line having a constant delay, whichhas drivers connected in series. Such a digital delay line may beintegrated on a semiconductor or may be assembled using a plurality ofintegrated circuits. FIG. 1 shows such a delay line.

The delay line in FIG. 1 is made up of drivers 1, 2, 3, 4, as well asfurther drivers which are connected in series. Each of the drivers has adelay time of Δt. After passing through a series connection ofn-drivers, a time delay of n*Δt is therefore achieved. The disadvantagehere is that, because of the great number of drivers necessary, acorrespondingly large silicon surface is needed. The use of such delaylines may therefore be limited to pulse radar systems for aviation andspace flight, as well as military applications.

SUMMARY OF THE INVENTION

An object of the exemplary embodiment and/or exemplary method of thepresent invention is to provide an improved digital delay line,particularly for use for radar-based distance measurements and/orrelative-speed measurements from a vehicle.

One advantage of the exemplary embodiment and/or exemplary method of thepresent invention is that, because of the recursive formation of adigital delay line according to the present invention, substantiallyfewer delay elements, and therefore a substantially smaller siliconsurface are necessary. For example, this allows for the integration of adigital delay line of the exemplary embodiment and/or exemplary methodof the present invention on an integrated circuit, e.g. an applicationspecific integrated circuit (ASIC), with a considerable reduction inproduction costs. The exemplary embodiment and/or exemplary method ofthe present invention thereby opens up further fields of application forradar-based distance measurements and relative-speed measurements,particularly in the field of automotive electronics.

According to one exemplary embodiment of the present invention, thedelay is adjustable within a predefined range, and specificallyadvantageously in linear fashion, the quantization being given by thedelay time of a single one of the delay elements used.

A further special advantage is the scaling ability, that is, if greaterdelay times are needed, this may be achieved by adding a furtherfeedback delay line. This should be achievable without developmentexpenditure and without reducing the accuracy.

Another advantage may be that the adjustable delay range may be setindependently of the resolution of the individual gate delay times. Thismeans that one no longer has to rely on the switching hysteresis of adigital gate for representing the entire delay range. Rather, theexemplary embodiment and/or exemplary method of the present inventionallows for the realization of a delay time of, in principle, any lengthby the cascading of feedback counters. The individual counters are madeup, for example, of series-connected, standardized logic gates such asshift registers. In this manner, parasitic effects are not applicable,such as, for example, nonlinearities when using an analog delay line,which are otherwise caused by the use of the switching hysteresis.

According to another exemplary embodiment of the present invention, an“in-system calibration” is carried out or performed to thusautomatically make an inexpensive adjustment. This may also be animportant advantage, particularly for applications in the field ofautomotive electronics.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 shows an available delay line, from the related art, having aconstant delay time.

FIG. 2 shows a block diagram of an exemplary embodiment of a digitaldelay line according to the present invention.

FIG. 3 shows a block diagram for the setting of the delay time.

FIG. 4 shows a diagram for illustrating the cascading of delay lines.

FIG. 5 shows a second exemplary embodiment of a digital delay line.

FIG. 6 shows a block diagram for representing the clocking of the shiftregisters.

FIG. 7 shows a block diagram of a circuit for the calibration of thedigital delay line.

FIG. 8 shows a block diagram of an electronic system having a digitaldelay line.

DETAILED DESCRIPTION

FIG. 2 shows a block diagram of a digital delay line. The digital delayline includes a delay line 1 having a number of delay elements 2. Thenumber of delay elements is, for example, eight, or may be another powerof two.

Delay elements 2 may be logic gates, each having a gate delay time ofΔt. Delay elements 2 are interconnected to form a ring. To travelthrough the ring formed by delay line 1 one time, a pulse 3 requires atime of n*Δt, if a number of n delay elements 2 is provided. At the sametime, time Δt is the smallest adjustable delay increment.

One of delay elements 2 has an output 4. Output 4 is connected to theclock input of a counter 5. Counter 5 is made up of logic gatesconnected in series. In the specific embodiment in FIG. 2, they areso-called D-registers 6. Counter 5 is thus a chain of shift registers.Output 4 is in each case connected to the clock inputs of D-registers 6.The D-input of first D-register 6 of counter 5 is also connected to amemory 7, in which the logical value one is stored. The travel timethrough one D-register 6 is less than the cycle time of delay line 1.

The output of last D-register 6 of counter 5 is fed back to the resetinputs of all D-registers 6 of counter 5. The reset pulse takes placesynchronously with a cycle time of delay line 1.

The digital delay line in FIG. 2 also includes further counters 8, 9, .. . As a general matter, further counters 8, 9, . . . have the same oressentially the same construction as counter 5. The output of lastD-register 6 of counter 5 is used for clocking subsequent counter 8. Thedata input of first D-register 6 of counter 8 is in turn connected tomemory 7, so that the logical value one is clocked into counter 8 uponreception of a clock signal from the output of last D-register 6 incounter 5.

It is also a corresponding case for counter 9, which receives the outputof last D-register 6 of counter 8 as a clock signal. In this way, theentire delay line can cascade.

During operation of the digital delay line, pulse 3 runs constantlythrough delay line 1. In so doing, pulse 3 is delayed by each delayelement 2 of delay line 1 by time interval Δt. Therefore, a clock signalis available at output 4 after time intervals n*Δt if delay line 1contains a number of n delay elements 2.

The result of this clock signal is that, at point of time n*Δt, thelogical value one is clocked into first D-register 6 of counter 5. Thus,if the number of D-registers 6 in counter 5 is likewise n, the logicalvalue one reaches last D-register 6 of counter 5 after a time intervalof n*n*Δt.

At this point of time, logical value one is clocked into firstD-register 6 of counter 8, since the output of last D-register 6 ofcounter 5 is used as the clock output for counter 8. At the same time,D-registers 6 of counter 5 are reset.

The logical value one then travels through counter 8 up to lastD-register 6 of counter 8 within a time interval of n*n*n*Δt. The caseis corresponding for counter 9, which is traversed by the logical valueone after time interval n*n*n*n*Δt.

By cascading further counters, in this way delays of any length may beachieved without this being associated with a loss in accuracy.

For a delay line having 512 delay increments, 512 delay elements arethus not needed, as in the related art, but rather, for example, onlyn=8 delay elements for the first delay line and two cascaded counters.Thus, instead of 512 delay elements, only a total of 24 elements areneeded.

A further advantage is that the expenditure from the standpoint ofcircuit engineering for the signal taps of the delay elements andcounting elements is also reduced accordingly. Each output of an elementmay be linked to a multiplexer terminal, so that an adjustable delaytime of the digital delay line is able to be queried. FIG. 3 shows asuitable circuit:

The circuit in FIG. 3 contains a multiplexer for each of the delay linesof the circuit in FIG. 2. Multiplexer 10 is connected with its inputs 11in each case to an output of one of delay elements 2 of delay line 1.The case is corresponding for multiplexer 12, which is connected withits inputs 13 to the outputs of D-registers 6 of counter 5.

It is the same for multiplexer 14, whose inputs 15 are connected toD-registers 6 of counter 8, as well as for further multiplexers, notshown in FIG. 3 for the sake of clarity, which in each case areallocated to a further counter 9, . . . Thus, each delay element of eachof the cascaded delay lines and counters is connected to an input of themultiplexer assigned to the respective line.

Multiplexers 10, 12, 14, . . . are controlled by a control 16. Thedesired delay time may be set via control 16.

Outputs 17, 18, 19, . . . of multiplexers 10, 12, 14, . . . are linkedto the inputs of an AND gate 17. AND gate 17 has an output 18 whichassumes the value logical one as soon as the delay time set via control16 has been reached.

For example, to set a delay time of 150*Δt, the output of sixth delayelement 2 of delay line 1, the output of second D-register 6 of counter5 and the output of second D-register 6 of counter 8 are selected, fromwhich the total delay time of 150*Δt is yielded from 6Δt+16Δt+128Δt. Inthis way, for example, 512 delay increments may be set in a steplessmanner using only 24 elements.

Output 18 of AND gate 17 is connected to a multiplier 19. The otherinput of multiplier 19 is connected to a signal source 20. The output ofmultiplier 19 is connected to evaluation unit 21. To determine whethersignal source 20 emits a signal after a certain delay time, theprocedure is as follows:

The outputs of delay elements 2 and 6, respectively, of the digitaldelay lines are selected via control 16 in accordance with the delaytime of interest. If signal source 20 emits the signal after the delaytime has elapsed, the result of the multiplying by multiplier 19 will belogical one; if the opposite is the case, that is, if the signal sourceeither emits no signal or does so at an earlier or later point of time,then the output of multiplier 19 remains logical zero.

This information is evaluated by evaluation unit 21, for example, forthe purpose of measuring the distance and/or differential speed. This isexplained in greater detail below.

FIG. 4 again illustrates the method of operation of a digital delay lineaccording to the present invention. In the exemplified case considered,the digital delay line is made up of three cascaded delay lines/countinglines, having in each case eight delay elements. The first delay linehas delay elements 22, each having a gate delay time of Δt. A singlecirculation of a pulse 23 through the feedback ring delay line formed bydelay elements 22 therefore requires a time duration of 8*Δt.

The counting line downstream of this delay line is therefore clocked attime intervals of 8*Δt. The circulation of a pulse through thisdownstream counting line thus requires a time duration of 8*8*Δt. For acirculation through the further downstream counting line, a timeduration of 8*8*8*Δt is needed.

FIG. 5 shows a further specific embodiment of the invention. Elements ofFIG. 5 which correspond to elements of FIG. 2 are identified using thesame reference numerals. In contrast to the specific embodiment in FIG.2, a synchronizing element 24 is located between output 4 of delayelement 2 and the input of D-register 6.

Synchronizing element 24 is used to prevent inaccuracies which maydevelop during the coupling of logical one into counter 5 because of theelectrical load of delay element 2. To that end, a pulse travels throughdelay line 1 once, so that after the first pass, logical one is presentvia synchronizing element 24 at the input of first D-register 6 ofcounter 5.

In a subsequent clocking of D-registers 6 of counter 5 via output 4,logical one is then clocked into counter 5, without the electricalloading of delay element 2 occurring at its output 4. Thus, in thisexemplary embodiment, to initialize the digital delay line, it isnecessary that the pulse first travel once through delay line 1.

FIG. 6 shows another exemplary embodiment for the interface betweendelay element 2, output 4 and synchronizing element 24, as well asD-registers 6 of counter 5. A lag unit 25 is located at output 4. Theoutput of lag unit 25 supplies clock signal 26. On the other hand, datasignal 27 is present at output 4.

In the exemplary embodiment considered here, synchronizing element 24and D-registers 6 are implemented by identical gates. Each gate has adata input D, a clock input Clk as well as a reset input RES. Data inputD of synchronizing element 24 is associated with data signal 27. Clockinput Clk of synchronizing element 24 is associated with clock signal26.

Data inputs D of D-registers 6 of counter 5 are each connected to theoutput of preceding D-register 6. First D-register 6 in counter 5, whichis shown in FIG. 6, is connected to the output of synchronizing element24. All the clock inputs of D-registers 6 of counter 5 are associatedwith clock signal 26.

When a pulse travels through delay element 2, this yields the pattern ofdata signal 27 shown in FIG. 6. The delay through lag unit 25 yields thepattern of clock signal 26. At the output of synchronizing element 24 isthen output signal 28, which at the same time is the input signal forfirst D-register 6 in counter 5.

After a further circulation of the pulse through delay line 1, a clocksignal 26 is emitted once more, so that the logical value one, which isrepresented by output signal 28, is then clocked directly into counter5. This procedure is repeated after each resetting of D-registers 6 ofcounter 5. A memory 7 (see FIG. 2) is thus not needed here.

FIG. 7 shows a calibration circuit for the digital delay line. Thecalibration circuit is made up of a microcontroller 29 which correspondsto control 16 of FIG. 3.

Microcontroller 29 is linked to digital delay line 30, in thatmicrocontroller 29 drives the multiplexers of digital delay line 30 (seemultiplexers 10, 12, 13, . . . of FIG. 3).

The calibration circuit also includes a calibration device 31 having alag element which is used as a reference standard. A delay time oft_(Dsetpoint) is predefined for the calibration. Microcontroller 29drives the multiplexers of digital delay line 30 accordingly. After timet_(Dactual), the digital delay line then emits a signal. At the sametime, calibration device 31 is also started, which emits a signal aftertime t_(Dcal). From the difference of t_(Dactual) and t_(Dsetpoint), aswell as time t_(Dcal), the calibration is then carried out inmicrocontroller 29.

FIG. 8 shows a block diagram of an electronic system in which thedigital delay line is used. The electronic system includes a transmitter32 for sending out a high-frequency radar pulse, as well as a receiver33 for receiving the reflected pulse. The high-frequency signal issupplied by a high-frequency generator 34 that, for example, emits ahigh-frequency signal having a frequency of 24 GHz. This signal isswitched to transmitter 32 when semiconductor switch 35 is closed.Switch 35 is closed by the emission of a signal from microcontroller 36which reaches the control input of switch 35 via pulse shaper 37.

In the same way, the signal emitted by microcontroller 36 is input intoa digital delay line 38 according to the exemplary embodiment and/orexemplary method of the present invention. The delay of delay line 38 isadjustable via control output 39 of microcontroller 36. When a number xof delay increments has been set by microcontroller 36, then, after timeduration x*Δt, delay line 38 emits a signal which, via further pulseshaper 37, reaches the control input of further switch 40 and closes itwith the time delay of x*Δt after the closing of switch 35.

In this manner, multiplier 41 is connected both to high-frequencygenerator 34 and to receiver 33. The output of multiplier 41 isconnected via amplifier 42 to an input of microcontroller 36. Whenmicrocontroller 36 receives a signal from multiplier 41, this means thatthe reflected pulse has been received by receiver 33 after thepropagation time of x*Δt. This means that an object is located at acorresponding distance. This information is transmitted frommicrocontroller 36 via line 43 to evaluation unit 44.

Microcontroller 36 may drive delay line 38 so that the delay iscontinually varied for successive high-frequency pulses, in order tocover a specific predefined distance range. Evaluation unit 44 may beused for implementing different applications, such as for ascertaining arelative speed, for initiating an automatic braking procedure when acollision looms, for the so-called adaptive cruise control or formonitoring the blind spot.

The reference numeral list is as follows:

delay line  1; delay element  2; pulse  3; output  4; counter  5;D-register  6; memory  7; counter  8; counter  9; multiplexer 10; input11; multiplexer 12; input 13; multiplexer 14; input 15; control 16; ANDgate 17; output 18; multiplexer 19; signal source 20; evaluation unit21; delay element 22; pulse 23; synchronizing element 24; lag unit 25;clock signal 26; data signal 27; output signal 28; microcontroller 29;digital delay line 30; calibration device 31; transmitter 32; receiver33; high-frequency generator 34; switch 35; microcontroller 36; pulseshaper 37; delay line 38; control output 39; switch 40; multiplier 41;amplifier 42; line 43; and evaluation unit 44.

1. A digital delay line comprising: a feedback delay line having a firstnumber of interlinked delay elements; at least one feedback counterhaving a second number of interlinked counting elements, the countingelements being clocked by one of the first delay elements; a firstmultiplexer arrangement for the delay elements whose inputs are coupledto outputs of the delay elements; a second multiplexer arrangement forthe counting elements whose inputs are coupled to outputs of thecounting elements; and an AND gate whose inputs are coupled to an outputof the first multiplexer arrangement and to an output of the secondmultiplexer arrangement.
 2. The digital delay line of claim 1, whereinthe first delay elements include drivers.